1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device capacitor, and more particularly, to a semiconductor device capacitor, and a method of manufacturing the same, wherein the concentration of the impurities inside a storage electrode of the capacitor decreases going upward from the bottom of the contact hole to the top of the storage electrode.
2. Description of the Related Art
The demand for increased integration of semiconductor devices typically requires an increase of the capacitance of a semiconductor device capacitor, and therefore, the structure of the semiconductor device capacitor is becoming more complicated. Among semiconductor memory devices, one unit cell of Dynamic Random Access Memory (DRAM) comprises a single capacitor and a single transistor, and the above-mentioned demand for increased integration of semiconductor devices requires the size of the unit cell be decreased, together with increasing the capacitance of the capacitor.
Therefore, various shapes of semiconductor device capacitors and various method of manufacturing the same have been developed in order to achieve a sufficient capacitance for the capacitor, even though the occupancy area of the capacitor is decreased. For example, a trench capacitor achieves the desired capacitance by digging deep into the inside of the semiconductor substrate. A simple stacked structure, such as a stack capacitor, provides a device structure with a high step-height. Then there are complicated structures such as a fin shape or cylinder shape which increase the surface area of the capacitor and provide a desired capacitance.
In the DRAM device, the memory capacity of the device is proportional to the capacitance of the capacitor, and the capacitance of the capacitor is proportional to the surface area of the storage electrode of the capacitor and the permittivity of the dielectric layer.
Therefore, many attempts and methods have been introduced to increase the capacitance with a highly-integrated semiconductor device, such as techniques for the formation of the storage electrode, the addition of following processes, and the formation of a dielectric layer having high permittivity, etc. For example, 1) a method of depositing a dielectric layer having a high permittivity, such as TiN and Ta.sub.2 O.sub.3 etc., after etching the polysilicon layer of the storage electrode; 2) a method of increasing the surface area of the capacitor by altering the etch types for the polysilicon layer of the storage electrode, etc.
However, the above methods of increasing the surface area of the capacitor alter the structure of the storage electrode rather than using the characteristics of the material itself as an ingredient of the storage electrode.
In one technique of increasing a capacitor's surface area, an HSG (Hemispherical Grain) layer, its surface being hemispherical-shaped, is formed as a polysilicon layer on the surface of the storage electrode. The size of one grain in the HSG layer is between 500 to 1000 .ANG.. So, the capacitance of the capacitor formed thereby can be increased by a factor of two.
At present, a representative structure for a DRAM device is a Capacitor Over Bit line (COB) structure, wherein a capacitor is formed on the bit line so as to increase the thickness of the storage electrode, and the HSG layer is formed on the storage electrode to increase the capacitance of the capacitor.
The method of manufacturing a semiconductor device capacitor having the COB structure is described below. First, a bit line is formed on a semiconductor substrate to be in communication with the drain region of the transistor, and an insulating material is deposited on the whole surface of the semiconductor substrate to insulate the bit line. Subsequently, the insulating material is partially removed so as to expose some portion of the source region of the transistor. The storage electrode is formed on the insulating material layer, and it is in communication with the source region of the transistor via the exposed portion on the source region.
FIGS. 1 and 2 are cross-sectional views to show the conventional method of forming a semiconductor device capacitor.
As shown in FIG. 1, contact holes 16 are formed on a semiconductor substrate 2 having a specific lower structure comprising insulating layers including a nitride layer 12 and an oxide layer 14, etc. After depositing an amorphous silicon (a-Si) layer on the whole surface of the semiconductor substrate 2, and carrying out a photo etching process, a storage electrode 18 of the capacitor is formed with a desired pattern.
The storage electrode 18 is in communication with the source region 4 of the transistor via the contact holes 16, and stores the information according to the charges transferred from the source region 4. The nitride layer 12 and the oxide layer 14 included in the lower structure of the semiconductor substrate 2 are called an interlayer dielectric layer.
In other words, a lower structure is formed on the semiconductor substrate 2, and contact holes 16 are formed on the contact portion with the source region by means of a typical photo etching process. Then, the storage electrode 18 is formed by depositing amorphous silicon (a-Si) as the material of the storage electrode 18 on the semiconductor substrate including the contact holes 16 by using a Low Pressure Chemical Vapour Deposition (LPCVD) method, and carrying out a photo etching process so as to form a desired pattern of the storage electrode 18.
The amorphous silicon (a-Si) as the storage electrode 18 is deposited by supplying and pyrolyzing silane (SiH.sub.4) gas and phosphine (PH.sub.3) gas at process temperature ranges of 500 to 530.degree. C. Preferably, the amorphous silicon (a-Si) is deposited by means of Low Pressure Chemical Vapour Deposition (LPCVD) method, for its favorable uniformity, impurity, and economic properties. The phosphorus (P) of the phosphine (PH.sub.3) gas functions as the impurity of the amorphous silicon (a-Si).
FIG. 2 is a cross-sectional view showing that the dielectric layer 22 and the plate electrode 24 are formed after forming the HSG layer 20 on the storage electrode 18. The formation of an HSG (Hemispherical Grain) layer is discussed, for example, in the reference by Watanabe et al. entitled "Hemispherical Grained Silicon Formation on In-Situ Phosphorus Doped Amorphous-Si Using The Seeding Method," (SSDM 1992, pp. 422-424). In particular, a hemispherical grain silicon layer can be formed at the transition temperature range of crystalline silicon and amorphous silicon through silicon migration so that its surface energy is stabilized.
The HSG layer 20 increases the surface area by a factor of as much as two or three. The HSG layer 20 is formed by means of the LPCVD method. First, after maintaining the process chamber at a temperature of 550.degree. C. and at 1 Torr, silicon-containing gas having an active surface reaction such as silane (SiH.sub.4) gas or desilane (Si.sub.2 H.sub.6) gas is supplied so as to create the nucleus formation on the surface of the storage electrode 18. Then, heat-treatment is applied so as to cause a thermal migration of the nucleus. Thus, the HSG layer 20 is formed having a rough surface.
Normally, the grain size of the HSG layer 20 varies depending on the concentration of the phosphorus (P) as an impurity in the amorphous silicon (a-Si) of the storage electrode 18. In other words, the grain size of the HSG layer 20 becomes larger when the concentration of the phosphorus (P) is reduced. However, in decreasing the concentration of the phosphorus (P) in order to increase the grain size of the HSG layer 20, the bulk resistance of the amorphous silicon of the storage electrode is increased, thereby degrading its function as the storage electrode. Further, the interface resistance of the amorphous silicon inside the contact hole 16 and the cell pad 8 is abruptly increased so that the operation speed of the device is decreased.
FIG. 3 is a graphical representation correlating the bulk resistance of the storage electrode to the interface resistance of the storage electrode and the cell pad at various impurity concentration levels.
The X-axis shows the bulk resistance values of the storage electrode 18, and Y-axis shows the interface resistance values of the storage electrode 18 and the cell pad 8. The dark points in the graph mean sample wafers. The circled portion A includes the sample wafers having low bulk resistance values and the circled portion B includes the sample wafers having high bulk resistance values.
Therefore, referring to FIG. 3, the lower the bulk resistance of the storage electrode 18 is, the lower the interface resistance of the storage electrode 18 and the cell pad 8 is.
In the conventional art, there has been no way to produce an HSG layer having large grains while at the same time producing a low value of interface resistance, because the concentration of the impurities inside the storage electrode has been uniformly provided during the formation of the storage electrode.